1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having a sharp step portion on the surface thereof, in which method a wiring pattern is formed on the surface with little dimensional error even if it is formed in the neighborhood of the step portion.
2. Description of the Related Art
Following the recent compact design of integrated circuit devices to be formed on a semiconductor substrate, the microstructure and high integration of elements constituting the integrated circuit devices have been also required.
In such a device as a dynamic RAM (DRAM), a one-transistor and one-capacitor structure is used for a memory cell, and data reception/transmission is performed by charging/discharging charges into/from the capacitor. Therefore, the advancement of the compact design of elements would increase the probability that the amount of charges to be accumulated in the capacitor is reduced and some malfunction occurs in data reading/writing operation.
In order to solve the above problem, it is effective to increase the amount of charges to be accumulated in the capacitor, and thus there is generally used a method of increasing the height of charging electrodes and also increasing the surface area of the charging electrodes, thereby ensuring the increased amount of charges to be accumulated. As a result, the height of the memory cell portion and the height of the peripheral circuit portion are different from each other, so that a sharp step occurs at the boundary between the memory cell portion and the peripheral circuit portion. The sharp step thus formed makes it very difficult to perform a patterning process of wires which will be formed in a subsequent process.
FIGS. 1 and 2 show a conventional DRAM. Specifically, FIGS. 1 and 2 are cross-sectional views showing a series of a manufacturing process of a DRAM cell which comprises a MOS capacitor and a MOS transistor.
FIG. 1 shows a boundary portion between a memory cell portion and a peripheral circuit portion. As shown in FIG. 1, field oxide films 2 which serves as element isolating regions are formed on a P-type semiconductor substrate 1, and a gate electrode 4 and source/drain N.sup.+ -type diffusion layers 3 which constitute a transistor are formed in the element region of the peripheral circuit portion.
Likewise, each transistor of the memory cell portion also comprises a gate electrode 4 and source/drain N.sup.+ -type diffusion layers 3. The gate electrode 4 is connected to a word line 10 which is formed by patterning an upper wiring layer 7 later. One of the N.sup.+ -type diffusion layers 3 is connected to a bit line 6 while the other N.sup.+ -type diffusion layer 3 is connected to accumulating electrodes 5 for accumulating charges. A plate electrode which serves as a counter electrode to the accumulating electrode 5 is omitted from the figures. Thereafter, an interlayer film 12 is formed to establish insulation between layers, so that a large, sharp step is formed between the memory cell portion and the peripheral circuit portion.
Thereafter, an upper wiring layer 7 is deposited to form the word line, and then a photoresist is spin-coated to subject the upper wiring layer 7 to a patterning process. At this time, since the large step exists between the memory cell portion and the peripheral circuit portion, the thickness of the photoresist layer is non-uniform in the neighborhood of the step. That is, the photoresist layer is thinner (e.g., T.sub.0, T.sub.1) at the upper side in the vicinity of the step (at the memory cell portion side) than the other portion and thicker (e.g., T.sub.3) at the lower side in the vicinity of the step (at the peripheral circuit portion side) than the other portion.
Thus, when the thickness of the photoresist layer is varied due to the step of the surface on which the photoresist layer is formed as shown in FIG. 1, the patterning process of the wirings causes dispersion of wiring dimension. That is, in an area where the thickness of the photoresist layer is equal to T.sub.2, the patterning can be performed at the wiring dimension A (micrometer) which is equal to the design value (in this case, A micrometer). However, when the design dimension of all mask patterns for preparing photoresist patterns, the dimension T.sub.0, T.sub.1 or T.sub.3 of the photoresist patterns of each of the upper and lower sides in the vicinity of the step portion is smaller than the design value A (micrometer) as shown in FIG. 1. That is, the following relationship is satisfied:
A (micrometer)&gt;B (micrometer)&gt;C(micrometer), PA1 A (micrometer)&gt;D (micrometer), PA1 A: mask pattern dimension=design dimension, PA1 A (micrometer) is obtained when the thickness of the photoresist layer is equal to T.sub.2 (micrometer), PA1 B (micrometer) is obtained when the thickness of the photoresist layer is equal to T.sub.0 (micrometer), PA1 C (micrometer) is obtained when the thickness of the photoresist layer is equal to T.sub.1 (micrometer), and PA1 D (micrometer) is obtained when the thickness of the photoresist layer is equal to T.sub.3 (micrometer). PA1 forming a wiring layer on the surface of the area containing vicinity of the step portion and the flat portion; PA1 forming a photoresist layer on the wiring layer; PA1 patterning the photoresist layer by using a photomask to form a photoresist pattern corresponding to the wirings; and PA1 etching the wiring layer by using the photoresist pattern to remove an exposed portion of the wiring layer and form the wirings, wherein the photomask has a first mask pattern corresponding to the photoresist pattern formed in the vicinity of the step portion at at least one of upper and lower portion sides of the step portion and a second mask pattern corresponding to the photoresist pattern formed in the flat portion, the first mask pattern having a dimension larger than a corresponding value of a predetermined dimension of corresponding wirings, the second mask pattern having a dimension equal to a corresponding value of a predetermined dimension of corresponding wirings.
In the above state, the upper wiring layer 7 is etched to form the word lines 10. FIG. 2 shows a state where the wiring layer 7 is etched and the patterned photoresist layer 9 is exfoliated. The dimension of the word lines 10 reflects the dimensional dispersion of the patterned photoresist layer 9, and thus the dimension of the word lines 10 in the vicinity of the step is smaller than the design dimension.
Furthermore, Japanese Patent Application Laid-open No. Hei-3-282545 discloses a semiconductor device having a groove portion 16 on the surface thereof. FIGS. 3 and 4 show this semiconductor device. When wirings 14 are patterned on a surface of a semiconductor device having a groove portion 16 as shown in FIG. 3, as the interval between a mask 17 and a photoresist layer is increased, the width of the photoresist pattern trends to be small. Therefore, an element forming pattern 20 of the mask 17 is designed so that it contains a rectangular portion 18 at both the end portions thereof and a curved or fat portion 19 of a large pattern width at the center portion thereof in accordance with the depth of the groove portion 16 as shown in FIG. 4.
Further, Japanese Patent Application Laid-open No. Hei-3-137647 discloses a semiconductor substrate 24 having steps as shown in FIG. 5. In this case, there is a large difference between the thickness 21 of the photoresist layer 23 at the upper side of the step and the thickness 22 of the photoresist layer 23 at the lower side of the step, and thus a dimensional difference of the patterned photoresist layer occurs. In the Japanese Patent Application laid-open No. Hei-3-137647, a countermeasure is taken by varying the correction amount of the mask dimension for patterning the photoresist layer between the pattern at the step upper side and the pattern at the step lower side.
The first problem of the above-mentioned art resides in that when a photoresist layer is patterned at the whole area under the condition that the wiring dimension which is coincident with the design value can be obtained at a flat portion, the wiring dimension in the vicinity of the step portion is smaller than that at the flat portion. This is because the thickness of the photoresist layer in the vicinity of the step portion is different from that at the flat portion.
The second problem of the above-mentioned art resides in that the resistance of wiring in the vicinity of the step portion increases to induce a lag of timing in the data reception/ transmission or the like, so that the quality and yield of the memory cell device are reduced. This is because only the wirings in the vicinity of the step portion are formed so that the dimension thereof is smaller than the design value.